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SPC560B50x Datasheet(PDF) 44 Page - STMicroelectronics |
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SPC560B50x Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 116 page ![]() Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 44/116 DocID14619 Rev 13 Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V. 3.14 Thermal characteristics 3.14.1 Package thermal characteristics IINJPAD SR Injected input current on any pin during overload condition — 55 mA IINJSUM SR Absolute sum of all injected input currents during overload condition — 50 50 TVDD SR VDD slope to ensure correct power up (6) —3.0(7) 250 x 103 (0.25 [V/µs]) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 4. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5. 1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Another ceramic cap of 10 nF with low inductance package can be added. 6. Guaranteed by device validation. 7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH). Table 14. Recommended operating conditions (5.0 V) (continued) Symbol Parameter Conditions Value Unit Min Max Table 15. LQFP thermal characteristics(1) Symbol C Parameter Conditions(2) Pin count Value Unit RJA CC D Thermal resistance, junction-to- ambient natural convection(3) Single-layer board - 1s 64 60 °C/W 100 64 144 64 Four-layer board - 2s2p 64 42 100 51 144 49 RJB CC D Thermal resistance, junction-to- board(4) Single-layer board - 1s 64 24 °C/W 100 36 144 37 Four-layer board - 2s2p 64 24 100 34 144 35 |
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