ADF4252BCPZ-R7 datasheet(5/30 Pages) AD

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Data Sheet

ADF4252

Rev. E | Page 5 of 30

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLIES

VDD1, VDD2, VDD3

2.7

3.3

DVDD

VDD1

VP1, VP2

VDD1

5.5

IDD3

RF + IF

RF Only

IF Only

5.5

Power-Down Mode

μA

RF NOISE AND SPURIOUS CHARACTERISTICS

Noise Floor

−141

dBc/Hz

At 20 MHz PFD frequency

In-Band Phase Noise Performance4

At VCO output

Lowest Spur Mode

−90

dBc/Hz

RFOUT = 1.8 GHz, PFD = 20 MHz

Low Noise and Spur Mode

−95

dBc/Hz

RFOUT = 1.8 GHz, PFD = 20 MHz

Lowest Noise Mode

−103

dBc/Hz

RFOUT = 1.8 GHz, PFD = 20 MHz

Spurious Signals

See the Typical Performance

Characteristics section

1 Operating temperature range = −40°C to +85°C.

2 Use a square wave for frequencies less than fMIN.

3 RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, VDD = 3 V, VP1 = 5 V, and VP2 = 3 V.

4 The in-band phase noise is measured with the EVAL-ADF4252EB2 evaluation board and the HP5500E phase noise test system. The spectrum analyzer provides the

REFIN for the synthesizer (fREFOUT = 10 MHz at 0 dBm). fOUT = 1.74 GHz, fREF = 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, VDD = 3.3 V, and VP = 5 V.

TIMING CHARACTERISTICS

VDD1 = VDD2 = VDD3 = DVDD = 3 V ± 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter1

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

ns min

LE setup time

ns min

DATA to CLOCK setup time

ns min

DATA to CLOCK hold time

ns min

CLOCK high duration

ns min

CLOCK low duration

ns min

CLOCK to LE setup time

ns min

LE pulse width

1 Guaranteed by design, but not production tested.

CLOCK

DATA

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

Figure 2. Timing Diagram

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