STM32W108HB datasheet(93/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose input/output

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8.1.7

Wake monitoring

The GPIOx_WAKER registers specify which GPIOs are monitored to wake the processor. If

a GPIO's wake enable bit is set in GPIOx_WAKER, then a change in the logic value of that

GPIO causes the STM32W108 to wake from deep sleep. The logic values of all GPIOs are

captured by hardware upon entering sleep. If any GPIO's logic value changes while in sleep

and that GPIO's GPIOx_WAKER bit is set, then the STM32W108 will wake from deep sleep.

(There is no mechanism for selecting a specific rising-edge, falling-edge, or level on a GPIO:

any change in logic value triggers a wake event.) Hardware records the fact that GPIO

activity caused a wake event, but not which specific GPIO was responsible. Instead,

software should read the state of the GPIOs on waking to determine the cause of the event.

The register GPIO_WAKEFR contains bits to enable digital filtering of the external wakeup

event sources: the GPIO pins, SC1 activity, SC2 activity, and IRQD. The digital filter

operates by taking samples based on the (nominal) 10 kHz LSI RC oscillator. If three

samples in a row all have the same logic value, and this sampled logic value is different from

the logic value seen upon entering sleep, the filter outputs a wakeup event.

In order to use GPIO pins to wake the STM32W108 from deep sleep, the GPIO_WAKE bit in

the WAKE_SEL register must be set. Waking up from GPIO activity does not work with pins

configured for analog mode since the digital logic input is always set to 1 when in analog

mode. Refer to Section 6: System modules on page 42 for information on the STM32W108's

power management and sleep modes.

8.2

External interrupts

The STM32W108 can use up to four external interrupt sources (IRQA, IRQB, IRQC, and

IRQD), each with its own top level NVIC interrupt vector. Since these external interrupt

sources connect to the standard GPIO input path, an external interrupt pin may

simultaneously be used by a peripheral device or even configured as an output. Analog

mode is the only GPIO configuration that is not compatible with using a pin as an external

interrupt.

External interrupts have individual triggering and filtering options selected using the

registers EXTIA_TSR, EXTIB_TSR, EXTIC_TSR, and EXTID_TSR. The bit field INTMOD of

the EXTIx_TSR register enables IRQx's second level interrupt and selects the triggering

mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3 for both edges; 4 for active high

level; 5 for active low level. The minimum width needed to latch an unfiltered external

interrupt in both level- and edge-triggered mode is 80 ns. With the digital filter enabled (the

FILTEN bit in the EXTIx_TSR register is set), the minimum width needed is 450 ns.

The register EXTI_PR is the second-level interrupt flag register that indicates pending

external interrupts. Writing 1 to a bit in the EXTI_PR register clears the flag while writing 0

has no effect. If the interrupt is level-triggered, the flag bit is set again immediately after

being cleared if its input is still in the active state.

Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other

two external interrupts, IRQC and IRQD, can use any GPIO pin. The EXTIC_CR and

EXTID_CR registers specify the GPIO pins assigned to IRQC and IRQD, respectively.

Table 16 shows how the EXTIC_CR and EXTID_CR register values select the GPIO pin

used for the external interrupt.

STM32W108HB Datasheet(PDF) 93 Page - STMicroelectronics

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