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STM32W108HB Datasheet(PDF) 38 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 278 page ![]() Embedded memory STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 38/278 Doc ID 16252 Rev 14 4.4 Memory protection unit The STM32W108 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The MPU controls access rights and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU. ST software configures the MPU in a standard configuration and application software should not modify it. The configuration is designed for optimal detection of illegal instruction or data accesses. If an illegal access is attempted, the MPU captures information about the access type, the address being accessed, and the location of the offending software. This simplifies software debugging and increases the reliability of deployed devices. As a consequence of this MPU configuration, accessing RAM and register bit-band address alias regions is not permitted, and generates a bus fault if attempted. |
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