STM32W108HB datasheet(32/278 Pages) STMICROELECTRONICS

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Embedded memory

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Flash may be programmed either through the Serial Wire/JTAG interface or through

bootloader software. Programming Flash through Serial Wire/JTAG requires the assistance

of RAM-based utility code. Programming through a bootloader requires specific software for

over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also

available preprogrammed into the FIB.

4.3

Random-access memory

The STM32W108 has 8/12/16 Kbytes of static RAM on-chip. The start of RAM is mapped to

address 0x20000000. Although the ARM® Cortex-M3 allows bit band accesses to this

address region, the standard MPU configuration does not permit use of the bit-band feature.

The RAM is physically connected to the AHB System bus and is therefore accessible to both

the ARM® Cortex-M3 microprocessor and the debugger. The RAM can be accessed for

both instruction and data fetches as bytes, half words, or words. The standard MPU

configuration does not permit execution from the RAM, but for special purposes, such as

programming the main Flash block, the MPU may be disabled. To the bus, the RAM appears

as 32-bit wide memory and in most situations has zero wait state read or write access. In

the higher CPU clock mode the RAM requires two wait states. This is handled by hardware

transparent to the user application with no configuration required.

4.3.1

Direct memory access (DMA) to RAM

Several of the peripherals are equipped with DMA controllers allowing them to transfer data

into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general

purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full

duplex so that a read and a write to RAM may be requested at the same time. Thus there

are six DMA channels in total.

The STM32W108 integrates a DMA arbiter that ensures fair access to the microprocessor

as well as the peripherals through a fixed priority scheme appropriate to the memory

bandwidth requirements of each master. The priority scheme is as follows, with the top

peripheral being the highest priority:

General Purpose ADC

Serial Controller 2 Receive

Serial Controller 2 Transmit

MAC

Serial Controller 1 Receive

Serial Controller 1 Transmit

STM32W108HB Datasheet(PDF) 32 Page - STMicroelectronics