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STM32W108HB Datasheet(PDF) 33 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Embedded memory Doc ID 16252 Rev 14 33/278 4.3.2 RAM memory protection The STM32W108 integrates two memory protection mechanisms. The first memory protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU) described in the Memory Protection Unit section. The MPU may be used to protect any area of memory. MPU configuration is normally handled by software. The second memory protection mechanism is through a fine granularity RAM protection module. This allows segmentation of the RAM into blocks where any block can be marked as write protected. An attempt to write to a protected RAM block using a user mode write results in a bus error being signaled on the AHB System bus. A system mode write is allowed at any time and reads are allowed in either mode. The main purpose of this fine granularity RAM protection module is to notify the stack of erroneous writes to system areas of memory. RAM protection is configured using a group of registers that provide a bit map. Each bit in the map represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for STM32W108CC and STM32W108CZ.When the bit is set the block is write protected. The fine granularity RAM memory protection mechanism is also available to the peripheral DMA controllers. A register bit is provided to enable the memory protection to include DMA writes to protected memory. If a DMA write is made to a protected location in RAM, a management interrupt is generated. At the same time the faulting address and the identification of the peripheral is captured for later debugging. Note that only peripherals capable of writing data to RAM, such as received packet data or a received serial port character, can generate this interrupt. 4.3.3 Memory controller The STM32W108xx allows the RAM and DMA protection to be controlled using the memory controller interface. The chip contains eight RAM protection registers and two DMA protection registers. In addition, the chip contains a register, RAM_CR, for enabling the protection of the memory. |
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