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DSP56367P Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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DSP56367P Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 100 page  External Memory Expansion Port (Port A) DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-29 Figure 3-17 DRAM Refresh Access 3.10.3 Arbitration Timings Table 3-14 Asynchronous Bus Arbitration Timing1, 2, 3 1 Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode. 2 If Asynchronous Arbitration mode is active, none of the timings in Table 3-14 is required. 3 In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-18. No. Characteristics Expression 150 MHz Unit Min Max 250 BB assertion window from BG input negation. 2 .5* Tc + 5 — 21.7 ns 251 Delay from BB assertion to BG assertion 2 * Tc + 5 18.3 — ns RAS CAS WR 157 163 162 162 190 170 165 189 177 AA0478 |
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