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DSP56367P Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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DSP56367P Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 100 page  Serial Host Interface (SHI) I2C Protocol Timing DSP56367 Technical Data, Rev. 2.1 3-42 Freescale Semiconductor Figure 3-30 SPI Slave Timing (CPHA = 1) 3.13 Serial Host Interface (SHI) I2C Protocol Timing Table 3-17 SHI I2C Protocol Timing Standard I2C No. Characteristics1, 2, 3 Symbol/ Expression Standard4, 5 Fast-Mode5, 6 Unit Min Max Min Max Tolerable spike width on SCL or SDA • Filters bypassed • Narrow filters enabled • Wide filters enabled — — — — 0 50 100 — — — 0 50 100 ns 171 SCL clock frequency FSCL — 100 — 400 kHz 171 SCL clock cycle TSCL 10 — 2.5 — µs 172 Bus free time TBUF 4.7 — 1.3 — µs 173 Start condition set-up time TSU;STA 4.7 — 0.6 — µs 174 Start condition hold time THD;STA 4.0 — 0.6 — µs SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) MISO (Output) MOSI (Input) MSB LSB MSB LSB HREQ (Output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 Valid Valid 148 147 146 152 149 157 AA0274 |
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