LQFP64 datasheet(7/90 Pages) STMICROELECTRONICS

7 / 90 page

SPC560D30x, SPC56040Dx

Introduction

Doc ID 16315 Rev 7

7/90

Introduction

1.1

Document overview

This document describes the device features and highlights the important electrical and

physical characteristics.

1.2

Description

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices

designed to be central to the development of the next wave of central vehicle body

controller, smart junction box, front module, peripheral body, door control and seat control

applications.

This family is one of a series of next-generation integrated automotive microcontrollers

based on the Power Architecture technology and designed specifically for embedded

applications.

The advanced and cost-efficient e200z0h host processor core of this automotive controller

family complies with the Power Architecture technology and only implements the VLE

(variable-length encoding) APU (auxiliary processing unit), providing improved code density.

It operates at speeds of up to 48 MHz and offers high performance processing optimized for

low power consumption. It capitalizes on the available development infrastructure of current

Power Architecture devices and is supported with software drivers, operating systems and

configuration code to assist with the user’s implementations.

The device platform has a single level of memory hierarchy and can support a wide range of

on-chip static random access memory (SRAM) and internal flash memory.

Table 2.

Pictus 512K device comparison

Feature

Device

SPC560D30L1

SPC560D30L3

SPC560D40L1

SPC560D40L3

CPU

e200z0h

Execution speed

Static – up to 48 MHz

Code flash memory

128 KB

256 KB

Data flash memory

64 KB (4 × 16 KB)

SRAM

12 KB

16 KB

eDMA

16 ch

ADC (12-bit)

16 ch

33 ch

16 ch

33 ch

CTU

16 ch

Total timer I/O(1)

eMIOS

14 ch, 16-bit

28 ch, 16-bit

14 ch, 16-bit

28 ch, 16-bit

– Type X(2)

2ch

5 ch

2ch

5 ch

– Type Y(3)

—9 ch

– Type G(4)

7ch

7 ch

7ch

7 ch

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