LQFP64 datasheet(71/90 Pages) STMICROELECTRONICS

71 / 90 page

SPC560D30x, SPC56040Dx

Electrical characteristics

Doc ID 16315 Rev 7

71/90

—

t

CSC

Internal delay between pad

associated to SCK and pad

associated to CSn in master

mode

Master mode

—

130(2)

—

t

ASC

Internal delay between pad

associated to SCK and pad

associated to CSn in master

mode for CSn1

1

Master mode

—

130(2)

2tCSCext

(3)

D CS to SCK delay

Slave mode

—

3tASCext

(4)

D After SCK delay

Slave mode

1/fDSPI + 5

—

4tSDC

SCK duty cycle

Master mode

—

tSCK/2

—

Slave mode

tSCK/2

—

5tA

D Slave access time

—

1/fDSPI +70

—

6tDI

D Slave SOUT disable time

—

7tPCSC

D PCSx to PCSS time

—

8tPASC

D PCSS to PCSx time

—

9tSUI

D Data setup time for inputs

Master mode

—

Slave mode

—

tHI

D Data hold time for inputs

Master mode

—

Slave mode

2(5)

——

tSUO

(6)

D Data valid after SCK edge

Master mode

—

Slave mode

—

tHO

(6)

D Data hold time for outputs

Master mode

—

Slave mode

—

Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns

Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad

The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in

DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

t

CSC to ensure positive tCSCext.

The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in

DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

t

ASC to ensure positive tASCext.

This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR.

SCK and SOUT configured as MEDIUM pad

Table 44.

DSPI characteristics(1) (continued)

No.

Symbol

Parameter

DSPI0/DSPI1

Unit

Min

Typ

Max

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