ST92F120 datasheet(13/324 Pages) STMICROELECTRONICS

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ST92F120 - GENERAL DESCRIPTION

Table 1. ST92F120 Power Supply Pins

Table 2. ST92F120 Primary Function Pins

Figure 8. Recommended Connections for VREG

Note : For future compatibility with shrinked versions, the VREG pins should be connected to a minimum

of 600 nF (total). Special care should be taken to minimize the distance between the ST9 microcontroller

and the capacitors.

Name

Function

VDD

Main Power Supply Voltage

( pins internally connected)

VSS

Digital Circuit Ground

(pins internally connected)

AVDD

Analog Circuit Supply Voltage

AVSS

Analog Circuit Ground

VTEST

Must be kept low in standard operating

mode

VREG

3V Regulator output

(on future versions,

i.e. ST92F124 and ST92F150)

Name

Function

Address Strobe

Data Strobe

Read/Write

OSCIN

Oscillator Input

OSCOUT

Oscillator Output

RESET

Reset to initialize the Microcontroller

HW0SW1

Watchdog HW/SW enabling selec-

tion

VPWO

J1850 JBLPD Output. On devices

without JBPLD peripheral, this pin

must not be connected.

300 nF

PQFP100

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