DS0147 datasheet(49/128 Pages) MICROCHIP

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5. This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS

models or shown in the figure Output Delay Measurement—Single-Ended Test Setup.

6. Emulated bidirectional interface.

6.2.2

Output Delay Measurement Methodology

The following section provides information about the methodology for output delay measurement.

Table 58 • Output Delay Measurement Methodology

VREF (V)

VMEAS (V)

CREF (pF)

RREF (Ω)

Description

Standard

1.65

PCIE 3.3 V

PCI

1.65

LVTTL 3.3 V

LVTTL

1.65

LVCMOS 3.3 V

LVCMOS33

1.25

LVCMOS 2.5 V

LVCMOS25

0.90

LVCMOS 1.8 V

LVCMOS18

0.75

LVCMOS 1.5 V

LVCMOS15

0.60

LVCMOS 1.2 V

LVCMOS12

1.25

VREF

Stub-series termi-

nated logic 2.5 V C-

lass I

SSTL25I

1.25

VREF

SSTL 2.5 V Class II

SSTL25II

0.9

VREF

SSTL 1.8 V Class I

SSTL18I

0.9

VREF

SSTL 1.8 V Class II

SSTL18II

0.75

VREF

SSTL 1.5 V Class I

SSTL15I

0.75

VREF

SSTL 1.5 V Class II

SSTL15II

0.675

VREF

SSTL 1.35 V Class I

SSTL135I

0.675

VREF

SSTL 1.35 V Class II

SSTL135II

0.75

VREF

High-speed

transceiver logic

(HSTL) 1.5 V Class I

HSTL15I

0.75

VREF

HSTL 1.5 V Class II

HSTL15II

0.675

VREF

HSTL 1.35 V Class I

HSTL135I

0.675

VREF

HSTL 1.35 V Class II

HSTL135II

0.6

VREF

HSTL 1.2 V Class I

HSTL12I

0.6

VREF

HSTL 1.2 V Class II

HSTL12II

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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