10

AT49LL080

3273C–FLASH–5/03

OUTPUT DISABLE: When the LPC is not selected through a LPC read or write cycle,

the LPC interface outputs (LAD[3:0]) are disabled and will be placed in a high-imped-

ance state.

Bus Abort

The Bus Abort operation can be used to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low, V

ory will tri-state the Input/Output Communication pins, LAD3 - LAD0 and the LPC state

machine will reset. During a write cycle, there is the possibility that an internal Flash

write or erase operation is in progress (or has just been initiated). If the LFRAME is

asserted during this time frame, the internal operation will not abort. The software must

send an explicit Flash command to terminate or suspend the operation. The internal

LPC state machine will not initiate a Flash write or erase operation until it has received

the last nibble from the chipset. This means that LFRAME can be asserted as late as

cycle 12 (Table 6) and no internal Flash operation will be attempted.

HARDWARE WRITE-PROTECT PINS TBL AND WP: Two pins are available with the

LPC to provide hardware write-protect capabilities.

The Top Sector Lock (TBL) pin is a signal, when held low (active), prevents program or

sector erase operations in the top sector of the device (sector 15) where critical code

can be stored. When TBL is high, hardware write protection of the top sector is disabled.

The write-protect (WP) pin serves the same function for all the remaining sectors except

the top sector. WP operates independently from TBL and does not affect the lock status

of the top sector.

The TBL and WP pins must be set to the desired protection state prior to starting a pro-

gram or erase operation since they are sampled at the beginning of the operation.

Changing the state of TBL or WP during a program or erase operation may cause

unpredictable results.

If the state of TBL or WP changes during a program suspend or erase suspend state,

the changes to the device’s locking status do not take place immediately. The sus-

pended operation may be resumed to successfully complete the program or erase

operation. The new lock status will take place after the program or erase operation

completes.

These pins function in combination with the register-based sector locking (to be

explained later). These pins, when active, will write-protect the appropriate sector(s),

regardless of the associated sector locking registers. (For example, when TBL is active,

writing to the top sector is prevented, regardless of the state of the Write Lock bit for the

top sector’s locking register. In such a case, clearing the write-protect bit in the register

will have no functional effect, even though the register may indicate that the sector is no

longer locked. The register may still be set to read-lock the sector, if desired.)