| Electronic Components Datasheet Search |
|
PCF5271CVM100 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
PCF5271CVM100 Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc |
|
43 / 56 page ![]() Preliminary Electrical Characteristics MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 43 Figure 10 shows an SDRAM read cycle. Figure 10. SDRAM Read Cycle Table 32. SDRAM Timing NUM Characteristic Symbol Min Max Unit D1 CLKOUT high to SDRAM address valid tCHDAV —9 ns D2 CLKOUT high to SDRAM control valid tCHDCV —9 ns D3 CLKOUT high to SDRAM address invalid tCHDAI 1.5 — ns D4 CLKOUT high to SDRAM control invalid tCHDCI 1.5 — ns D5 SDRAM data valid to CLKOUT high tDDVCH 4— ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.5 — ns D71 NOTES: 1 D7 and D8 are for write cycles only. CLKOUT high to SDRAM data valid tCHDDVW —9 ns D82 CLKOUT high to SDRAM data invalid tCHDDIW 1.5 — ns A[23:0] RAS D[31:0] ACTV NOP PALL NOP RAS[1:0] READ Column SD_CKE 0 SDWE CAS[3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D1 D2 D4 D6 D5 D4 D4 1 DACR[CASL] = 2 CAS 1 NOP D4 Row D3 D2 D2 D2 D2 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |