PCF5271CVM100 datasheet(17/56 Pages) FREESCALE

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Modes of Operation

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

— Partial drive strength (Default)

— Full drive strength

•

Clock mode:

— Normal PLL with external crystal

— Normal PLL with external clock

— 1:1 PLL Mode

— External oscillator mode (no PLL)

•

Chip Select Configuration:

— PADDR[7:5] configured as chip select(s) and/or address line(s)

– PADDR[7:5] configured as A23-A21 (default)

– PADDR configured as CS6, PADDR[6:5] as A22-A21

– PADDR[7:6] configured as CS[6:5], PADDR5 as A21

– PADDR[7:5] configured as CS[6:4]

5.1.1

Chip Configuration Pins

Table 3. Configuration Pin Descriptions

Chip Configuration

Function

Pin State/Meaning

Comments

RCON

Chip configuration

enable

1 Disabled

0 Enabled

Active low: if asserted, then all

configuration pins must be driven

appropriately for desired operation

D16

Select chip

operating mode

1Master

0 Reserved

D20, D19

Select external boot

device data port size

00,11 External (32-bit)

10 External (8-bit)

01 External (16-bit)

Value read defaults to 32-bit

D21

Select output pad

drive strength

1Full

0 Partial

CLKMOD1,

CLKMOD0

Select clock mode

00 External clock mode (no

PLL)

01 1:1 PLL mode

10 Normal PLL with

external clock reference

11 Normal PLL with crystal

clock reference

VDDPLL must be supplied if a PLL

mode is selected

PCF5271CVM100 Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

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