MPC875CVR133 datasheet(3/84 Pages) FREESCALE

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MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

Features

•

Thirty-two address lines

•

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory

devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes–256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

•

Two Fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS

that interface through MII and/or RMII interfaces

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1™ Std. test access port (JTAG)

•

Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

IEEE 802.11i® standard, and iSCSI processing. Available on the MPC875, the security engine

contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The

CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric key cipher

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