SSD1850 datasheet(39/56 Pages) ETC

39 / 56 page

SSD1850/51 Series

Rev 1.2

01/2003

SOLOMON

TABLE 3a. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=2.7V, VSS=0V)

Symbol

Parameter

Min

Typ

Max

Unit

tcycle

Clock Cycle Time (write cycle)

100

tAS

Address Setup Time

tAH

Address Hold Time

tDSW

Write Data Setup Time

tDHW

Write Data Hold Time

tDHR

Read Data Hold Time

tOH

Output Disable Time

tACC

Access Time

PWCSL

Chip Select Low Pulse Width (read RAM)

Chip Select Low Pulse Width (read command)

Chip Select Low Pulse Width (write)

PWCSH

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write)

Rise Time

Fall Time

Valid Data

cycle

DSW

DHR

ACC

D/C

0 -D7

Valid Data

0-D 7

(Write data to driv er)

(Read data f rom driv er)

DHW

CSL

CSH

R/W

Figure 1a. Parallel 6800-series Interface Timing Characteristics (PS0=H, PS1=H)

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