ATXMEGA8E5 datasheet(92/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 92

ATxmega32E5/16E5/8E5

36.13.5

Internal Phase Locked Loop (PLL) Characteristics

Table 36-24. Internal PLL Characteristics

Note:

The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.13.6

External Clock Characteristics

Figure 36-3. External Clock Drive Waveform

Table 36-25. External Clock used as System Clock without Prescaling

Note:

The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

fIN

Input frequency

Output frequency must be within fOUT

0.4

MHz

fOUT

Output frequency (1)

VCC= 1.6 - 1.8V

VCC= 2.7 - 3.6V

128

Start-up time

µs

Re-lock time

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

1/tCK

Clock Frequency (1)

VCC = 1.6 - 1.8V

MHz

VCC = 2.7 - 3.6V

tCK

Clock Period

VCC = 1.6 - 1.8V

83.3

VCC = 2.7 - 3.6V

31.5

tCH

Clock High Time

VCC = 1.6 - 1.8V

30.0

VCC = 2.7 - 3.6V

12.5

tCL

Clock Low Time

VCC = 1.6 - 1.8V

30.0

VCC = 2.7 - 3.6V

12.5

tCR

Rise Time (for maximum frequency)

VCC = 1.6 - 1.8V

VCC = 2.7 - 3.6V

tCF

Fall Time (for maximum frequency)

VCC = 1.6 - 1.8V

VCC = 2.7 - 3.6V

tCK

Change in period from one clock cycle to the next

tCH

tCL

tCK

tCH

VIL1

VIH1

tCR

tCF

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