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ATXMEGA8E5 Datasheet(PDF) 17 Page - Microchip Technology |
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ATXMEGA8E5 Datasheet(HTML) 17 Page - Microchip Technology |
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17 / 153 page  2018 Microchip Technology Inc. Data Sheet Complete DS40002059A-page 17 ATxmega32E5/16E5/8E5 8. Memories 8.1 Features Flash program memory One linear address space In-system programmable Self-programming and boot loader support Application section for application code Application table section for application code or data storage Boot section for application code or bootloader code Separate read/write protection lock bits for all sections Built in fast CRC check of a selectable flash program memory section Data memory One linear address space Single-cycle access from CPU SRAM EEPROM Byte and page accessible Memory mapped for direct load and store I/O memory Configuration and status registers for all peripherals and modules Four bit-accessible general purpose registers for global variables or flags Bus arbitration Deterministic handling of priority between CPU, EDMA controller, and other bus masters Separate buses for SRAM, EEPROM, and I/O memory Simultaneous bus access for CPU and EDMA controller Production signature row memory for factory programmed data ID for each microcontroller device type Serial number for each device Calibration bytes for factory calibrated peripherals User signature row One flash page in size Can be read and written from software Content is kept after chip erase 8.2 Overview The AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data mem- ory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in “Ordering Information” on page 8”. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. 8.3 Flash Program Memory The AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash mem- ory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. |
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