ATXMEGA8E5 datasheet(16/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 16

ATxmega32E5/16E5/8E5

7.7

Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing tempo-

rary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that

are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instruc-

tions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the

stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and

the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address

0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be

two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory,

the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more

than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by

three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from sub-

routine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one

when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for

up to four instructions or until the next I/O memory write.

7.8

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register

file supports the following input/output schemes:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient

address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash pro-

gram memory.

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