AM79C970AVCW datasheet(52/219 Pages) AMD

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P R E L I M I N A R Y

Am79C970A

Preemption During Burst Transaction

When the PCnet-PCI II controller operates in burst

mode, it only performs a single transaction per bus mas-

tership period, where transaction is defined as one ad-

dress phase and one or multiple data phases. The

central arbiter can remove

GNT at any time during the

transaction. The PCnet-PCI II controller will ignore the

deassertion of

GNT and continue with data transfers, as

long as the PCI Latency Timer is not expired. When the

Latency Timer is ZERO and

GNT is deasserted, the

PCnet-PCI II controller will finish the current data phase,

deassert

FRAME, finish the last data phase and release

the bus. If EXTREQ (BCR18, bit 8) is cleared to ZERO, it

will immediately assert

REQ to regain bus ownership as

soon as possible. If EXTREQ is set to ONE,

REQ will

stay asserted. When the preemption occurs after the

counter has counted down to ZERO, the PCnet-PCI II

controller will finish the current data phase, deassert

FRAME, finish the last data phase and release the bus.

Note that it is important for the host to program the PCI

Latency Timer according to the bus bandwidth require-

ment of the PCnet-PCI II controller. The host can deter-

mine this bus bandwidth requirement by reading the PCI

MAX_LAT and MIN_GNT registers.

The figure below assumes that the PCI Latency Timer

has counted down to ZERO on clock 7.

19436A-24

FRAME

CLK

IRDY

TRDY

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

234

DATA

PAR

REQ

DATA

PAR

GNT

Figure 21. Preemption During Burst Transaction

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