AM79C970AVCW datasheet(89/219 Pages) AMD

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AMD

Am79C970A

Table 10. GPSI Pin Configuration

PCnet-PCI II

Controller

C-LANCE

Controller

Expansion

GPSI Function

GPSI I/O Type

GPSI Pin

Pin Number

ROM Pin

Collision

CLSN

ERD3

Receive Clock

RCLK

RXCLK

ERD1

Receive Data

RXDAT

ERD0

Receive Enable

RENA

RXEN

ERD2

Transmit Clock

TCLK

TXCLK

ERD4

Transmit Data

TXDAT

ERD7

Transmit Enable

TENA

TXEN

ERD6

Note that the XTAL1 input must always be driven with a

clock source, even if GPSI mode is to be used. It is not

necessary for the XTAL1 clock to meet the normal fre-

quency and stability requirements in this case. Any fre-

quency between 8 MHz and 20 MHz is acceptable.

However, voltage drive requirements do not change.

When GPSI mode is used, XTAL1 must be driven for

several reasons:

s The default H_RESET configuration for the PCnet-

PCI II controller is AUI port selected and until GPSI

mode is selected, the XTAL1 clock is needed for

some internal operations (namely, RESET).

s The XTAL1 clock drives the EEPROM read opera-

tion, regardless of the network mode selected.

s The XTAL1 clock determines the length the internal

S_RESET caused by the read of the Reset register,

regardless of the network mode.

Note that if a clock slower than 20 MHz is provided at the

XTAL1 input, the time needed for EEPROM read and

the internal S_RESET will increase.

External Address Detection Interface

The External Address Detection Interface (EADI) is pro-

vided to allow external address filtering. It is selected by

setting the EADISEL bit in BCR2 to ONE. This feature is

typically utilized for terminal servers, bridges and/or

router products. The EADI interface can be used in con-

junction with external logic to capture the packet desti-

nation address from the serial bit stream as it arrives at

the PCnet-PCI II controller, compare the captured ad-

dress with a table of stored addresses or identifiers, and

then determine whether or not the PCnet-PCI II control-

ler should accept the packet.

The EADI interface outputs are delivered directly from

the NRZ decoded data and clock recovered by the

Manchester decoder or input into the GPSI port. This al-

lows the external address detection to be performed in

parallel with frame reception and address comparison in

the MAC Station Address Detection (SAD) block of the

PCnet-PCI II controller.

SRDCLK is provided to allow clocking of the receive bit

stream into the external address detection logic. Note

that when the 10BASE-T port is selected, transitions on

SRDCLK will only occur during receive activity. When

the AUI or GPSI port is selected, transitions on SRDCLK

will occur during both transmit and receive activity. Once

a received frame commences and data and clock are

available from the decoder, the EADI logic will monitor

the alternating (1,0) preamble pattern until the two

ONEs of the Start Frame Delimiter (SFD, 10101011 bit

pattern) are detected, at which point the SFBD output

will be driven HIGH.

The SFBD signal will initially be LOW. The assertion of

SFBD is a signal to the external address detection logic

that the SFD has been detected and that subsequent

SRDCLK cycles will deliver packet data to the external

logic. Therefore, when SFBD is asserted, the external

address matching logic should begin de-serialization of

the SRD data and send the resulting destination ad-

dress to a Content Addressable Memory (CAM) or other

address detection device. In order to reduce the amount

of logic external to the PCnet-PCI II controller for multi-

ple address decoding systems, the SFBD signal will

toggle at each new byte boundary within the packet,

subsequent to the SFD. This eliminates the need for ex-

ternally supplying byte framing logic.

SRD is the decoded NRZ data from the network. This

signal can be used for external address detection. Note

that when the 10BASE-T port is selected, transitions on

SRD will only occur during receive activity. When the

AUI or GPSI port is selected, transitions on SRD will oc-

cur during both transmit and receive activity.

The

EAR pin should be driven LOW by the external ad-

dress comparison logic to reject a frame.

If an address match is detected by comparison with

either the Physical Address or Logical Address Filter

registers contained within the PCnet-PCI II controller or

the frame is of the type “Broadcast”, then the frame will

be accepted regardless of the condition of

EAR. When

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