AM79C970AVCW datasheet(72/219 Pages) AMD

72 / 219 page

AMD

P R E L I M I N A R Y

Am79C970A

update the current RDTE status with the end of frame

(ENP) indication set, write the message byte count

(MCNT) for the entire frame into RMD2 and overwrite

the “current” entries in the CSRs with the “next” entries.

Media Access Control

The Media Access Control (MAC) engine incorporates

the essential protocol requirements for operation of a

compliant Ethernet/802.3 node, and provides the inter-

face between the FIFO sub-system and the Manchester

Encoder/Decoder (MENDEC).

This section describes operation of the MAC engine

when operating in half-duplex mode. When operating in

half-duplex mode, the MAC engine is fully compliant to

Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard

1990 Second Edition) and ANSI/IEEE 802.3 (1985).

When operating in full-duplex mode, the MAC engine

behavior

changes

described

the

section

“Full-Duplex Operation”.

The MAC engine provides programmable enhanced

features designed to minimize host supervision, bus

utilization, and pre- or post- message processing.

These include the ability to disable retries after a colli-

sion, dynamic FCS generation on a frame-by-frame ba-

sis, automatic pad field insertion and deletion to enforce

minimum frame size attributes, automatic re-transmis-

sion without reloading the FIFO, and automatic deletion

of collision fragments.

The two primary attributes of the MAC engine are:

s Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

s Media Access Management

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit and Receive Message Data

Encapsulation

The MAC engine provides minimum frame size enforce-

ment

for

transmit

and

receive

frames.

When

APAD_XMT (CSR, bit 11) is set to ONE, transmit mes-

sages will be padded with sufficient bytes (containing

00h) to ensure that the receiving station will observe an

information field (destination address, source address,

length/type, data and FCS) of 64 bytes. When

ASTRP_RCV (CSR4, bit 10) is set to ONE, the receiver

will automatically strip pad bytes from the received mes-

sage by observing the value in the length field, and strip-

ping excess bytes if this value is below the minimum

data

size

(46

bytes).

Both

features

can

independently over-ridden to allow illegally short (less

than 64 bytes of frame data) messages to be transmitted

and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred into

or out of main memory.

Framing

The MAC engine will autonomously handle the con-

struction of the transmit frame. Once the transmit FIFO

has been filled to the predetermined threshold (set by

XMTSP in CSR80), and access to the channel is cur-

rently permitted, the MAC engine will commence the 7

byte preamble sequence (10101010b, where first bit

transmitted is a 1). The MAC engine will subsequently

append

the

Start

Frame

Delimiter

(SFD)

byte

(10101011b) followed by the serialized data from the

transmit FIFO. Once the data has been completed, the

MAC engine will append the FCS (most significant bit

first) which was computed on the entire data portion of

the frame. The data portion of the frame consists of des-

tination address, source address, length/type, and

frame data. The user is responsible for the correct order-

ing and content in each of these fields in the frame.

The receive section of the MAC engine will detect an in-

coming preamble sequence and lock to the encoded

clock. The internal MENDEC will decode the serial bit

stream and present this to the MAC engine. The MAC

will discard the first 8 bits of information before search-

ing for the SFD sequence. Once the SFD is detected, all

subsequent bits are treated as part of the frame. The

MAC engine will inspect the length field to ensure mini-

mum frame size, strip unnecessary pad characters (if

enabled), and pass the remaining bytes through the re-

ceive FIFO to the host. If pad stripping is performed, the

MAC engine will also strip the received FCS bytes, al-

though normal FCS computation and checking will oc-

cur. Note that apart from pad stripping, the frame will be

passed unmodified to the host. If the length field has a

value of 46 or greater, all frame bytes including FCS will

be passed unmodified to the receive buffer, regardless

of the actual frame length.

If the frame terminates or suffers a collision before 64

bytes of information (after SFD) have been received, the

MAC engine will automatically delete the frame from

the receive FIFO, without host intervention. The

PCnet-PCI II controller has the ability to accept

runt

packets

for

diagnostics

purposes

and

proprietary networks.

Destination Address Handling

The first 6 bytes of information after SFD will be inter-

preted as the destination address field. The MAC engine

provides facilities for physical (unicast), logical (multi-

cast) and broadcast address reception.

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