80960JD datasheet(34/61 Pages) INTEL

34 / 61 page

PRELIMINARY

80960JD

TBSOV2

All Outputs (Non-Test) Valid Delay

(1, 10)

TBSOF2

All Outputs (Non-Test) Float Delay

(1, 10)

BSIS2

Input Setup to TCK — All Inputs (Non-

Test)

TBSIH2

Input Hold from TCK — All Inputs (Non-

Test)

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-

nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 3 of 3)

Symbol

Parameter

Min

Max

Units

Notes

80960JD Datasheet(PDF) 34 Page - Intel Corporation