80960JD datasheet(6/61 Pages) INTEL

6 / 61 page

PRELIMINARY

80960JD

Figure 2. 80960JD Block Diagram

Programmable

Bus

Control Unit

Interrupt Controller

Control

Address/

Instruction Sequencer

Physical Region

Configuration

Interrupt

Port

1 Kbyte

Data RAM

Memory

Interface

Execution

Multiply

Unit

Divide

Unit

Memory-Mapped

Data Bus

Global / Local

SRC2

DEST

SRC1

address

Control

effective

Constants

Generation

Unit

Address

32-bit Address

32-bit Data

Bus Request

Queues

and

Two 32-Bit

Timers

8-Set

Local Register Cache

PLL, Clocks,

Power Mgmt

Boundary Scan

Controller

TAP

CLKIN

128

32-bit buses

address / data

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

4 KByte Instruction Cache

Two-Way Set Associative

2 Kbyte Direct

Mapped Data

Cache

2.1

80960 Processor Core

The 80960Jx family is a scalar implementation of the

80960

Core

Architecture.

Intel

designed

this

processor core as a very high performance device

that is also cost-effective. Factors that contribute to

the core’s performance include:

• Core operates at twice the bus speed (80960JD

only)

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

• Efficient instruction pipeline minimizes pipeline

break latency

• Register and resource scoreboarding allow

overlapped instruction execution

• 128-bit register bus speeds local register caching

• 4 Kbyte two-way set associative, integrated

instruction cache

• 2 Kbyte direct-mapped, integrated data cache

• 1 Kbyte integrated data RAM delivers zero wait

state program data

2.2

Burst Bus

A 32-bit high-performance bus controller interfaces

the 80960JD to external memory and peripherals.

The BCU fetches instructions and transfers data at

the rate of up to four 32-bit words per six clock

cycles. The external address/data bus is multiplexed.

80960JD Datasheet(PDF) 6 Page - Intel Corporation

80960JD Datasheet(HTML) 6 Page - Intel Corporation

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