MC56F81663 datasheet(58/73 Pages) NXP

58 / 73 page

11.5.2 12-bit Digital-to-Analog Converter (DAC) parameters

NOTE

RLD = 3 kΩ and CLD = 400 pF, unless otherwise specified.

Table 29. DAC parameters

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

DC Specifications

Resolution

bits

Settling time1

At output load

RLD = 3 kΩ

CLD = 400 pF

Range of input digital words: 410 to

3891

—

1 (high-

speed

mode)

2 (low-

speed

mode)

µs

Power-up time

Time from release of PWRDWN

signal until DACOUT signal is valid

tDAPU

—

µs

Accuracy

Integral non-linearity

Range of input digital words:

410 to 3891 ($19A - $F33)

INL

—

+/- 3

+/- 4

LSB

Differential non-linearity

Range of input digital words:

410 to 3891 ($19A - $F33)

DNL

—

+/- 0.5

+/- 1

LSB

Monotonicity

> 6 sigma monotonicity,

< 3.4 ppm non-monotonicity

guaranteed

—

Offset error

Range of input digital words:

410 to 3891 ($19A - $F33)

VOFFSET

—

+/- 25

+ /- 43

Gain error

Range of input digital words: 410 to

3891 ($19A - $F33)

EGAIN

—

+/- 0.5

+/- 1.5

DAC Output

Output voltage range

Within 40 mV of either VSSA or VDDA

VOUT

VSSA +

0.04 V

—

VDDA - 0.04

AC Specifications

Signal-to-noise ratio

SNR

—

Spurious free dynamic

range

SFDR

—

-72

—

Effective number of bits

ENOB

—

bits

IDD from VDDA

average IDD of VDDA (IDD varies with

DAC input word)

IDDA

—

3.2

—

1. When DAC output is fed to other internal peripherals, the settling time is much shorter.

11.5.3 OPAMP electrical specifications

System modules

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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