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SPC572L64F2 Datasheet(PDF) 40 Page - STMicroelectronics |
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SPC572L64F2 Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 112 page  Electrical characteristics SPC572Lx 40/112 DocID027866 Rev 5 Figure 10. PLL integration PLL0 IRCOSC XOSC PLL0_PHI1 PLL0_PHI0 Table 20. PLL0 electrical characteristics Symbol C Parameter Conditions Value Unit Min Typ Max fPLL0IN SR — PLL0 input clock(1),(2) —8 — 44 MHz ΔPLL0IN SR — PLL0 input clock duty cycle(1) —40 — 60 % fPLL0VCO CC P PLL0 VCO frequency — 600 — 1250 MHz fPLL0PHI0 CC P PLL0 output frequency — 4.762 — 80 MHz fPLL0PHI1 CC P PLL0 output frequency — 4.762 — 100 MHz tPLL0LOCK CC P PLL0 lock time — — — 110 µs |ΔPLL0PHI0SPJ| CC T PLL0_PHI0 single period jitter fPLL0IN = 20 MHz (resonator) fPLL0PHI0 = 400 MHz, 6-sigma pk-pk —— 200 ps |ΔPLL0PHI1SPJ| CC T PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) fPLL0PHI1 = 40 MHz, 6- sigma pk-pk —— 300(3) ps ΔPLL0LTJ CC T PLL0 output long term jitter(3) fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz 10 periods accumulated jitter (80 MHz equivalent frequency), 6-sigma pk-pk —— ± 250 ps 16 periods accumulated jitter (50 MHz equivalent frequency), 6-sigma pk-pk —— ± 300 ps long term jitter (< 1 MHz equivalent frequency), 6-sigma pk-pk —— ± 500 ps IPLL0 CC C PLL0 consumption FINE LOCK state — — 5 mA fPLL0FREE CC D VCO free running frequency —35 — 400 MHz |
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