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ST7FLCD1 Datasheet(PDF) 65 Page - STMicroelectronics |
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ST7FLCD1 Datasheet(HTML) 65 Page - STMicroelectronics |
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65 / 95 page ![]() 65/95 ST7FLCD1 Display Data Channel Interfaces (DDC) Random address read: The master performs a dummy write to load the data address into the pointer LSB. Then the master sends a RESTART condition followed by a read Device Address (RW = 1). Sequential address read: This mode is similar to the current and random address reads, except that the master DOES acknowledge the data byte for the DDC2B Interface to output the next byte in sequence. To terminate the read operation the master must NOT acknowledge the last data byte and must generate a STOP condition. The data output are issued from consecutive memory addresses. End of communication: Upon a detection of NACK or STOP conditions at the end of a read transfer, the bit ENDCF is set and an interrupt is generated if ENDCE is set. Figure 38: Read Sequences DATA OUT DEV ADDR SDA ADDR ADDR + 1 Addr. Pointer DATA ADDR. DEV ADDR SDA XXXXh ADDR Addr. Pointer ADDR + 1 DATA OUT DEV ADDR DATA OUT 1 DEV ADDR SDA ADDR Addr. Pointer DATA OUT 2 DATA OUT n ADDR + n -1 ADDR + 1 ADDR + n Current Address Read Random Address Read Sequential Address Read ENDCF flag is set ENDCF flag is set ENDCF flag is set or or or |
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