PSD413A2 datasheet(64/123 Pages) STMICROELECTRONICS

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PSD4XX Family

9.4 Memory Block

The PSD4XX provides EPROM memory for code storage and SRAM memory for scratch

pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and

are defined by the user in the PSDsoft Software. Figure 32 shows the organization of the

Memory Block.

The PSD4XX family uses Zero-power memory techniques that place memory into Standby

Mode between MCU accesses. The memory becomes active briefly after an address

transition, then delivers new data to the outputs, latches the outputs, and returns to standby.

This is done automatically and the designer has to do nothing special to benefit from this

feature. Both the EPROM and SRAM have this feature.

9.4.1 EPROM

The PSD4XX provides three EPROM densities: 256Kbit, 512Kbit, or 1Mbit. The EPROM

is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals

(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for

microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as

16K x 16, 32K x 16 or 64K x 16.

9.4.2 SRAM

The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled

by chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.

This back-up mode is invoked when the VCC voltage drops under the Vstdby voltage by

approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and cannot be

lower than 2.7 volts.

9.4.3 Memory Select Map

The EPROM and SRAM chip select equations are defined in the ABEL file in terms of

address and other DPLD inputs. The memory space for the EPROM chip select

(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB, or 32KB) it is

selecting.

The following rules govern how the internal PSD4XX memory selects/space are defined:

t The EPROM blocks address space cannot overlap

t SRAM, internal I/O and Peripheral I/O space cannot overlap

t SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with

priority given to SRAM or I/O. The portion of EPROM which is overlapped

cannot be accessed.

The Peripheral I/O space refers to memory space occupied by peripherals when Port A is

configured in the Peripheral I/O Mode.

The PSD4XX

Architecture

(cont.)

PSD413A2 Datasheet(PDF) 64 Page - STMicroelectronics