PSD413A2 datasheet(87/123 Pages) STMICROELECTRONICS

87 / 123 page

PSD4XX Family

Explanation of AC Symbols for Non ZPLD Timing.

Example:

t AVLX Time from Address Valid to ALE Invalid.

A – Address

L – Logic Level Low or ALE

T – R/W

C – Power Down

N – Reset

t – Time

D– Input Data

P – Port Signal

V – Valid

E –E

Q – Output Data

X – No Longer a Valid Logic Level

H – Logic Level High

R – WR, UDS, LDS, DS, IORD, PSEN

Z – Float

I – Interrupt

S – Chip Select

-70

-90*

-15

EPROM_CMiser

Symbol

Parameter

Conditions

Min Max Min Max Min Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 3)

tLXAX

Address Hold Time

(Note 3)

tAVQV

Address Valid to Data

Valid

(Note 3)

150

Add 10

t SLQV

CS Valid to Data Valid

100

150

Add 10

RD to Data Valid

8/16-Bit Bus

(Note 1)

t RLQV

RD to Data Valid 8-Bit

Bus, 8031 Separate

(Note 2)

Mode

t RHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width

(Note 1)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time

to Enable

810

tELTL

R/W Hold Time After

Enable

In 16-Bit Data Bus

tAVPV

Address Input Valid to

Mode (Note 9)

Address Output Delay

In 8-Bit Data Bus

Mode (Note 9)

Read Timing (5 V ± 10% Versions)

NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals.

2. RD and PSEN have the same timing for 8031 mode.

3. Any input used to select an internal PSD4XX function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

*The -90 speed is available only on Industrial Temperature Range product.

13.8 Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions)

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