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PSD413A2 Datasheet(PDF) 68 Page - STMicroelectronics |
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PSD413A2 Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 123 page ![]() PSD4XX Family 65 PSD4XX Family The PSD4XX Architecture (cont.) Figure 34. Port A In Peripheral I/O Mode RD PSEL0 PSEL1 D0 – D7 WR PA0 – PA7 9.4.5 Peripheral I/O The Peripheral I/O Mode is one of the operating modes of Port A. In this mode, Port A is connected to the data bus of peripheral devices. Port A is enabled only when the microcontroller is accessing the devices, otherwise the Port is tri-stated. This feature enables the microcontroller to access external devices without requiring buffers and decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode. The memory address space occupied by the devices are defined by two signals: PSEL0 and PSEL1. The signals are direct outputs from the Decoding PLD (DPLD). Whenever any of the signals is active, the Port A driver is enabled, and the direction of the data flow is determined by the RD/WR signals. The Peripheral I/O Mode and the peripheral select signals are configured and defined in the PSDsoft Software (see the section on I/O Port for configuration). The PIO bit in the VM Register (see Table 17) also needs to be set to “1” by the user to initialize the Peripheral I/O Mode. The Peripheral I/O mode can be used, for example, in DMA applications where the microcontroller does not support DMA operations, such as tri-stating the address/data bus. Figure 35 shows a block diagram of a microcontroller and PSD4XX based design that makes use of this mode. In this application, the microcontroller has a multiplexed bus which is connected to the ADIO port. The C and D ports connect to the peripheral address bus and are both configured in Address Out Mode. Port A is configured in the Peripheral I/O mode and is connected to the peripheral data bus. Ports B and E are used to generate control signals. During normal activity, the microcontroller has access to any peripheral (memory or I/O device) through the PSD4XX device. When there is a DMA request, the microcontroller tri-states the address bus on Ports C and D by writing a “0” to the port Direction Registers. The DMA controller then takes over the data and address buses after receiving acknowledgement from the microcontroller. |
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