PSD413A2 datasheet(73/123 Pages) STMICROELECTRONICS

73 / 123 page

PSD4XX Family

9.5.2 Other Power Saving Options

The PSD4XX provides additional power saving options. These options, except the SRAM

Standby Mode, can be enabled/disabled by setting up the corresponding bit in the PMMR.

t EPROM

The EPROM power consumption in the PSD is controlled by bit 3 in the

PMMR0 – EPROM CMiser. Upon reset the CMiser bit is OFF. This will cause the

EPROM to be ON at all times as long as CSI is enabled (low). The reason this mode is

provided is to reduce the access time of the EPROM by 10 ns relative to the low power

condition when CMiser is ON. If CSI is disabled (high) the EPROM will be deselected

and will enter standby mode (OFF) overriding the state of the CMiser.

If CMiser is set (ON) then the EPROM will enter the standby mode when not selected.

This condition can take place when CSI is high or when CSI is low and the EPROM is

not accessed. For example, if the MCU is accessing the SRAM, the EPROM will be

deselected and will be in low power mode.

An additional advantage of the CMiser is achieved when the PSD is configured in the

by 8 mode (8 bit data bus). In this case an additional power savings is achieved in the

EPROM (and also in the SRAM) by turning off 1/2 of the array even when the EPROM

is accessed (the array is divided internally into odd and even arrays).

The power consumption for the different EPROM modes is given in the DC

Characteristics table under ICC (DC) EPROM Adder.

t SRAM Standby Mode

The SRAM has a dedicated supply voltage VSTBY that can be used to connect a battery.

When VCC becomes lower than VSTBY –0.6 then the PSD will automatically connect

the VSTBY as a power source to the SRAM. The SRAM Standby Current (ISTBY) is

typically 0.5 µA.

SRAM data retention voltage VDF is 2 V minimum.

t Zero Power ZPLD

ZPLD power/speed is controlled by the ZPLD_Turbo bit (bit 4) in the PMMR0.

After reset the ZPLD is in Turbo mode and runs at full power and speed. By setting the

bit to “1”, the Turbo mode is disabled and the ZPLD is consuming Zero Power current if

the inputs are not switching for an extended time of 70 ns. The propagation delay time

will be increased by 10ns after the Turbo bit is set to “1” (turned off) if the inputs change

at a frequency of less than 15 MHz.

The PSD4XX

Architecture

(cont.)

PSD413A2 Datasheet(PDF) 73 Page - STMicroelectronics