PSD413A2 datasheet(70/123 Pages) STMICROELECTRONICS

70 / 123 page

PSD4XX Family

9.5 Power Management Unit

The PSD4XX provides many power saving options. By configuring the PMMRs

(Power Management Mode Registers), the user can reduce power consumption. Table 18

shows the bit configuration of the PMMR0 and PMMR1. The microcontroller is able to

control the power consumption by changing the PMMR bits at run time.

9.5.1 Standby Mode

There are two Standby Modes in the PSD4XX:

t Power Down Mode

t Sleep Mode

9.5.1.1 Power Down Mode

In this mode, the internal devices are shut down except for the I/O ports and the ZPLD.

There are three ways the PSD4XX can enter into the Power Down Mode: by controlling

the CSI input, by activating the Automatic Power Down (APD) Logic and the ZPLD, or when

none of the inputs are changing and the Turbo bit is off.

t The CSI

The CSI input pin is an active low signal. When low, the signal selects and enables the

PSD4XX. The PSD4XX enters into Power Down Mode immediately when the signal

turns high. This signal can be controlled by the microcontrollers, external logic or it can

be grounded. The CSI input turns off the internal bus buffers in Standby Mode. The

address and control signals from the microcontroller are blocked from entering the ZPLD

as inputs.

t The APD Logic

The APD unit enables the user to enter a power down mode independent of controlling

the CSI input. This feature eliminates the need for external logic (decoders and latches)

to power down the PSD. The APD unit concept is based on tracking the activity on the

ALE pin. If the APD unit is enabled and ALE is not active, the 4-bit APD counter starts

counting and will overflow after 15 clocks, generating a PD (Power Down) signal

powering down the PSD. If sleep mode is enabled, then PD signal will also activate the

sleep mode. Immediately after ALE starts pulsing the PSD will get out of the power down

or sleep mode.

The operation of APD is controlled by the PMMR (see Figure 36a). PMMR1 bit 0 selects

the source of the APD counter clock. After reset the APD counter clock is connected to

PE7 (APD CLK) on the PSD. In order to guarantee that the APD will not overflow there

should be less than 15 APD clocks between two ALE pulses. If CLKIN frequency is

adequate, then it can be connected to the APD and PE7 is used for other functions.

The next step is to select the ALE power down polarity. Usually, MCUs entering power

down will freeze their ALE at logic high or low. By programming bit 1 of PMMR0 the

power down polarity can be defined for the APD. If the APD detects that the ALE is in

the power down polarity for 15 APD counter clocks then the PSD will enter a power

down mode. To enable the APD operation, bit 2 in the PMMR0 should be set high.

9.5.1.2 Sleep Mode

The Sleep Mode is activated if the SLEEP EN bit, the APD EN bit, and the ALE Polarity bit

in the PMMR are set, and the APD Counter has overflowed after 15 clocks (see Figure 36).

In Sleep Mode the PSD4XX consumes less power than the Power Down Mode.

In this mode, the ZPLD still monitors the inputs and responds to them. As soon as the ALE

starts pulsing, the PSD4XX exits the Sleep Mode.

The PSD access time from Sleep Mode is specified by tLVDV1. The ZPLD response time to

an input transition is specified by tLVDV2.

The PSD4XX

Architecture

(cont.)

PSD413A2 Datasheet(PDF) 70 Page - STMicroelectronics

PSD413A2 Datasheet(HTML) 70 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL