REV. M

Page 11

September 1998

AS3502

1) DIGITAL CONTROL REGISTER

This register controls the master clock divider, the enabling of the transmit channel, the enabling of thereceive

channel and the PCM format.

DC

D7

D6

D5

D4

D3

D2

D1

D0

Name

A/LIN

ENRX

ENTX

DIV3

DIV2

DIV1

DIV0

X

Default

0

0

0

0

0

0

0

X

Bit No

Symbol

Name and Description

D7

A/LIN

A-Law / Linear Select. In default mode or when set to Low 16-bit linear PCM format is

selected. When set to High 8-bit A-Law PCM format is selected.

D6

ENRX

Enable Receive Channel. When set to High the Receive Channel including the selected

output driver, the master clock divider and the Receive PCM interface are enabled.

When set to Low the Receive Channel will be powered down.

D5

ENTX

Enable Transmit Channel. When set to High the Transmit Channel including the se-

lected microphone input, the master clock divider and the Transmit PCM interface are

enabled. When set to Low the Transmit Channel will be powered down.

D4- D1

DIV3-DIV0 Master Clock Prescaler Setting Bits.

DIV3 DIV2 DIV1 DIV0 State

Master Clock Frequency

0

0

0

0

÷1

2.048 MHz

0

0

0

1

÷2

4.096 MHz

0

0

1

0

÷3

6.144 MHz

0

0

1

1

÷4

8.192 MHz

0

1

0

0

÷5

10.240 MHz

0

1

0

1

÷6

12.288 MHz

0

1

1

0

÷7

14.336 MHz

0

1

1

1

÷8

16.386 MHz

1

0

0

0

÷9

18.432 MHz

2) ANALOGUE CONTROL REGISTER

The Analogue Control Register enables the output drivers and the muting of the receive voice channel. Further it

allows to monitor clipping in both the transmit and the receive channel for software based automatic gain control.

AC

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

0

LOOP

CLIPRX

CLIPTX

ENEP

ENSPK

NOV

Default

0

0

0

0

0

0

0

0