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DP83849CVS/NOPB Datasheet(PDF) 26 Page - Texas Instruments |
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DP83849CVS/NOPB Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 100 page ![]() 25 www.national.com Table 5. Typical MDIO Frame Format Figure 4. Typical MDC/MDIO Read Operation Figure 5. Typical MDC/MDIO Write Operation 3.4.3 Serial Management Preamble Suppression The DP83849C supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) deter- mines that all PHYs in the system support Preamble Sup- pression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. The DP83849C requires a single initialization sequence of 32 bits of preamble following hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Pre- amble Suppression is supported. While the DP83849C requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subse- quent transaction. A minimum of one idle bit between man- agement transactions is required as specified in the IEEE 802.3u specification. 3.4.4 Simultaneous Register Write The DP83849C incorporates a mode which allows simulta- neous write access to both Port A and B register blocks at the same time. This mode is selected by setting bit 15 of RMII and Bypass Register (RBR, address 17h) in Port A. As long as this bit remains set, subsequent writes to Port A will write to registers in both ports. Register reads are unaf- fected. Each port must still be read individually. MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle> Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle> MDC MDIO 00 0 11 110 0 00 000 (STA) Idle Start Opcode (Read) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z MDIO (PHY) Z Z Z 0 0 0 1 1 0 0 0 1 0 0 0000 0 0 Z Idle Z Z MDC MDIO 00 0 11 11 0 0 0 0 000 (STA) Idle Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z 0 0 0 0 00 0 0 0 0 0 000 Z Idle 10 0 0 Z Z |
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