IMX6SDLCEC datasheet(49/169 Pages) NXP

49 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Figure 9. MLB 6-Pin Pipeline Diagram

Table 34 shows the AC parameters for MLB I/O.

4.8

Output Buffer Impedance Parameters

This section defines the I/O impedance parameters of the i.MX 6Solo/6DualLite processors for the

following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes

•LVDS I/O

•MLB I/O

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 10).

Table 34. I/O AC Parameters of MLB PHY

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Differential pulse skew1

1 t

SKD = | tPHLD -tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

tSKD

Rload = 50

between padp

and padn

——

0.1

Transition Low to High Time2

2 Measurement levels are 20-80% from output voltage.

tTLH

——

Transition High to Low Time

tTHL

——

MLB external clock Operating Frequency

fclk_ext

—

102.4

MHz

MLB PLL clock Operating Frequency

fclk_pll

—

307.2

MHz

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