EM357-RTR datasheet(150/240 Pages) ETC2

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EM351 / EM357

9.4 Interrupts

Each timer has its own top-level NVIC interrupt. Writing 1 to the INT_TIMx bit in the INT_CFGSET register

enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. Chapter

11, Interrupt System describes the interrupt system in detail.

Several kinds of timer events can generate a timer interrupt, and each has a status flag in the INT_TIMxFLAG

INT_TIMTIF – set by a rising edge on an external trigger, either edge in gated mode

INT_TIMCCRyIF –set by a channel y input capture or output compare event

INT_TIMUIF – set by a UEV

Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture mode, reading the

TIMx_CCRy register will also clear the INT_TIMCCRyIF bit.

The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request a top-level NVIC

timer interrupt. Only the events whose bits are set to 1 in INT_TIMxCFG can do so.

If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already set, the corresponding

capture/compare missed flag is set in the INT_TMRxMISS register. Clear a bit in the INT_TMRxMISS register by

writing a 1 to it.

9-30

120-035X-000D

Preliminary

EM357-RTR Datasheet(PDF) 150 Page - List of Unclassifed Manufacturers