ADAU1977WBCPZ-R7 datasheet(22/64 Pages) AD

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ADAU1977

Data Sheet

Rev. A | Page 22 of 64

The threshold can be set using the SHT_G_TRIP bits, Bits[3:2]

of Register 0x17 (see Table 16).

Table 16.

SHT_G_TRIP

(Register 0x17, Bits[3:2])

Short to Ground Threshold

0.2 × VREF

0.133 × VREF

0.1 × VREF

0.266 × VREF

Microphone Terminal Short Circuited

When both input terminals are shorted, both the AINxP and

AINxN input terminals are at the same voltage—around

MICBIAS/2. Any voltage between the set thresholds is reported

as a fault. The upper and lower threshold voltages can be set

using the SHT_T_TRIP bits, Bits[7:6] of Register 0x17 (see

Table 17).

The following equations can be used to calculate the upper and

lower thresholds:

Upper Threshold = MICBIAS(0.5 + x)

Lower Threshold = MICBIAS(0.5 − x)

where x can be set using the SHT_T_TRIP bits, Bits[7:6] of

Table 17.

SHT_T_TRIP

(Register 0x17, Bits [7:6])

0.035

0.017

0.071

Reserved

Microphone Terminals Open

In the event that any of the input terminals becomes open

circuited, AINxP is pulled to MICBIAS and AINxN is pulled to

a common ground. When the AINxP terminal is at a voltage

that is higher than the short to the MICBIAS threshold (set

using Bits[5:4] of Register 0x17) and the AINxN terminal

voltage is at a voltage that is less than the short to the ground

threshold (set using Bits[3:2] of Register 0x17), a fault is

reported. The fault cannot indicate which terminal is open

circuited because any terminal that is open circuited pulls AINxP

to MICBIAS and AINxN to a common ground.

FAULT Pin

The FAULT pin is an output pin that can be programmed to be

active high or active low logic using the IRQ_POL bit (Bit 4 of

IRQ_DRIVE bit (Bit 5 of Register 0x15) to drive always or to drive

only during a fault and is otherwise set to high-Z. The fault status

is registered in the IRQ_RESET bit (Bit 6 of Register 0x15). The

IRQ_RESET bit is a latched bit and is set in the event of a fault

and cleared only after the fault status bit is read.

Fault Timeout

To prevent the false triggering of a fault event, the fault timeout

adjust bits (Bits[5:4] of Register 0x18) are provided. These bits

can be used to set the time that the fault needs to persist before

being reported. The timeout can be set to 0 ms, 50 ms, 100 ms,

or 150 ms using the FAULT_TO bits (Bits[5:4] of Register 0x18).

The default value is 100 ms. A fault is recorded only if the

condition persists for more than a set minimum timeout.

Fault Masking

The faults can be masked to prevent triggering an interrupt

on the FAULT pin. Fault masking can be set using Bits[6:0] of

Table 18. Fault Masking

Fault

AINxP

AINxN

Short to Battery

Yes

Short to MICBIAS

Yes

Short to Ground

Yes

Short Between Positive and Negative Inputs

Yes

Open Input

Yes

When a fault mask bit is set, it is applied to all the channels.

There is no individual fault mask available per channel using this

bit. To mask individual channels, use the DIAG_MASK[4:1] bits

(Bits[3:0] of Register 0x15).

Diagnostics Sequence

The sequence shown in Figure 23 is recommended for reading

the faults reported by diagnostics.

Figure 23. Diagnostics Sequence

NORMAL

FAULT EVENT

IRQ TO

SYSTEM MICRO

FAULT

TIMEOUT

IRQ TO

SYSTEM MICRO

FAULT

TIMEOUT

IRQ TO

SYSTEM MICRO

FAULT

TIMEOUT

IRQ TO

SYSTEM MICRO

FAULT

TIMEOUT

IRQ TO

SYSTEM MICRO

I2C SEQUENCE

NORMAL

FAULT

TIMEOUT

AINx+/

AINx–

FAULT

I2C

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