LAN9730 datasheet(49/222 Pages) MICROCHIP

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DS00001946A-page 49

LAN9730/LAN9730i

4.4

FIFO Controller (FCT)

The FIFO controller uses a 28 kB internal SRAM to buffer RX and TX traffic. 20 kB are allocated for received Ethernet-

USB traffic (RX buffer), while 8 kB are allocated for USB-Ethernet traffic (TX buffer). Bulk-Out packets from the USB

controller are directly stored into the TX buffer. The FCT is responsible for extracting Ethernet frames from the USB

packet data and passing the frames to the MAC. Ethernet frames are directly stored into the RX buffer and become the

basis for Bulk-In packets. The FCT passes the stored data to the UTX in blocks typically 512 bytes in size.

4.4.1

RX PATH (ETHERNET -> USB)

The 20 kB RX FIFO buffers Ethernet frames received from the TLI. The UTX extracts these frames from the FCT to form

USB Bulk-In packets. The host drivers will ultimately reassemble the Ethernet frames from the USB packets.

The FCT manages the writing of data into the RX FIFO through the use of two pointers - the rx_wr_ptr and the rx_wr_h-

d_ptr. The rx_wr_ptr is used to write Ethernet frame data into the FIFO. The rx_wr_hd_ptr points to the location prior to

the first DWORD of the frame. It is used to write the RX Status Word received from the TLI, upon completion of a frame

transaction. This status word contains status information associated with the frame and the frame transaction.

Figure 4-4 illustrates how a frame is stored in the FIFO, along with pointer usage.

When the RX TLI signals that it has data ready, the RX TLI controller starts passing the RX packet data to the FCT. The

FCT updates the RX FIFO pointers as the data is written into the FIFO. The last transfer from the TLI is the RX Status

Word.

The FCT may insert 0-3 bytes at the start of the Ethernet frame. The value of the RX Data Offset (RXDOFF) field of the

Hardware Configuration Register (HW_CFG) determines the number of bytes inserted.

A received Ethernet frame is not visible to the UTX until the complete frame, including the RX Status Word, has been

written into the RX FIFO. This is due to the fact that the frame may have to be removed via a rewind (pointer adjustment),

in case of an error. Such is the case when a FIFO overflow condition is detected as the frame is being received. The

FCT may also be configured to rewind errored frames. Refer to Section 4.4.1.1, "RX Error Detection" for further details.

FIGURE 4-4:

RX FIFO STORAGE

RX Status Word

RX Ethernet

Frame 0

RX Status Word

RX Ethernet

Frame 1

rx_rd_ptr

rx_wr_hd_ptr

RX Ethernet

Frame 2

rx_wr_ptr

After the complete

Ethernet frame is written,

the size and status is

updated at the location

pointed to by the write

head pointer.

The write head pointer will

then advance to the

starting location for the

next Ethernet frame.

The read head pointer is

used for implementing

rewinds of USB packets.

rx_rd_hd_ptr

USB

Packet 0

USB

Packet 1

USB

Packet 2

USB

Packet 3

FIFO data is available for

transmit only after a

complete Ethernet frame is

received and stored.

Therefore, the RX FIFO

size will not reflect partially

received packets.

RX FIFO Size

Byte padding inserted by

the FCT. This amount is

determined by

RXDOFF[1:0]

Additional padding may be

inserted by the UTX.

The unused bytes in the

first and last DWORDs are

ignored by the host.

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