WM9713 datasheet(53/111 Pages) WOLFSON

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Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MUL

1 (Mute)

Mute SPKL

1: Mute (OFF)

0: No Mute (ON)

ZCL

Left zero cross enable

0: Change gain immediately

1: Change gain only on zero crossings,

or after time-out

13:8

SPKLVOL

000000

(0dB)

SPKL Volume

000000: 0dB (maximum)

000001: -1.5dB

… (1.5dB steps)

011111: -46.5dB

1xxxxx: -46.5dB

MUR

1 (Mute)

Mute SPKR

1: Mute (OFF)

0: No Mute (ON)

ZCR

Right zero cross enable

0: Change gain immediately

1: Change gain only on zero crossings,

or after time-out

02h

Speaker

Volume

5:0

SPKRVOL

00000

(0dB)

SPKR Volume

Similar to SPKLVOL

Table 36 SPKL / SPKR PGA Control

Note:

For BTL speaker drive, it is recommended that both PGAs have the same gain setting.

AUXILLARY OUTPUTS – OUT3 AND OUT4

The OUT3 and OUT4 outputs (pins 37 and 33) are designed to drive a loudspeaker load down to 8

Ω

and can also be used as line outputs and headphone outputs. They are designed to drive an 8

Ω load

AC coupled or in a BTL (capless) configuration and can be used as a midrail buffer to drive the

headphone outputs in a capless DC configuration. The available input sources are INV1/2 and Vmid

(see Table 37).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:2

OUT3

00 (Vmid)

OUT3 input source select

00: Vmid

01: no i/p (ZH if buffer disabled)

10: INV1

11: unused

1Ch

Output PGA

Mux Select

1:0

OUT4

00 (Vmid)

OUT4 input source select

00: Vmid

01: no i/p (ZH if buffer disabled)

10: INV2

11: unused

Table 37 OUT3 / OUT4 PGA Input Source

The signal volume on OUT3 and OUT4 can be independently adjusted under software control by

writing to register 06h.

When not in use OUT3 and OUT4 can be powered down using the Powerdown register bits OUT3

and OUT4 (register 3Eh, bits [11:12]). To minimise pops and clicks when the PGA is powered down /

up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures

the same DC level is maintained on the output pin throughout.

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