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WM9713 Datasheet(PDF) 93 Page - Wolfson Microelectronics plc |
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WM9713 Datasheet(HTML) 93 Page - Wolfson Microelectronics plc |
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93 / 111 page  Preliminary Technical Data WM9713L 1 PTD, March 2004, Rev 2.2 93 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 15 BB 0 (linear) Selects linear bass control or adaptive bass boost 12 BC 0 (low) Selects bass cut-off frequency 11:8 BASS 1111 (OFF) Controls bass intensity 6 DAT 0 (OFF) Enables 6dB pre-DAC attenuation 4 TC 0 (high) Selects treble cut-off frequency 20h 3:0 TRBL 1111 (OFF) Controls treble intensity Audio DACs, Tone Control / Bass Boost Register 20h controls the bass and treble response of the left and right audio DAC (but not AUXDAC). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 15:14 MICCMPSEL 00 (mics) Selects input function for MIC2A/COMP1 and MIC2B/COMP2 13:12 MPASEL 00 (MIC1) Selects input to MICA preamp (from MIC1, MIC2A, MIC2B) 11:10 MPABST 00 (12dB) Controls MICA preamp gain boost 9:8 MPBBST 00 (12dB) Controls MICB preamp gain boost 7 MBOP2EN 0 (Off) Enables microphone bias output path to pin 12 6 MBOP1EN 1 (On) Enables microphone bias output path to MICBIAS 5 MBVOL 0 (0.9xAVDD) Selects microphone bias voltage 4:2 MCDTHR 000 (100uA) Controls microphone current detect threshold 22h 1:0 MCDSCTHR 00 (600uA) Controls microphone short-circuit detect threshold Analogue Inputs, Microphone Input Register 22h controls the microphone input configuration and microphone bias and detect configuration. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 4 JIEN 0 (OFF) Jack insert detect enable 3:2 DCDRVSEL 00 (AC) Output PGA source for headphone DC reference (default is AC coupled – no source selected) 24h 1:0 EARSPKSEL 00 Ear speaker source select (default is no source selected) Analogue Audio Outputs Register 24h controls the output volume mapping on headphone jack insertion. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 14 PR6 1 (OFF) Disables all output PGAS 13 PR5 1 (OFF) Disables internal clock 12 PR4 1 (OFF) Disables AC-link interface (external clock off) 11 PR3 1 (OFF) Disables VREF, input PGAs, DACs, ADCs, mixers and outputs 10 PR2 1 (OFF) Disables input PGAs and mixers 9 PR1 1 (OFF) Disables stereo DAC 8 PR0 1 (OFF) Disables stereo ADCs and record mux PGA 3 REF 0 Read-only bit, indicates VREF is ready (inverse of PR2) 2 ANL 0 Read-only bit, indicates analogue mixers are ready (inverse of PR3) 1 DAC 0 Read-only bit, indicates stereo DAC is ready (inverse of PR1) 26h 0 ADC 0 Read-only bit, indicates stereo ADC is ready (inverse of PR0) Power Management Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit blocks depends on both register 24h AND registers 3Ch and 3Eh. |
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