WM9713 datasheet(97/111 Pages) WOLFSON

97 / 111 page

Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

MONO

0 (Off)

Enables fast power for MONO output

SPKL

0 (Off)

Enables fast power for SPKL output

SPKR

0 (Off)

Enables fast power for SPKR output

HPL

0 (Off)

Enables fast power for HPL output

HPR

0 (Off)

Enables fast power for HPR output

OUT3

0 (Off)

Enables fast power for OUT3 output

42h

OUT4

0 (Off)

Enables fast power for OUT4 output

Analogue

Audio

Outputs,

Power-Up

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

14:1

SEXT[6:4]

000 (div 1)

Defines clock division ratio for Hi-fi block: 000=f;

001=f/2; ... ; 111=f/8

11:8

SEXT[3:0]

0000 (div 1)

Defines clock division ratio for PCM interface and

voice DAC: 0000=f; 0001=f/1; … ; 1111=f/16

CLKSRC

1 (ext clk)

Selects between PLL clock and External clock

5:3

PENDIV

000 (div 16)

Sets PENADC clock divisor: 000=f/16; 001=f/12;

010=f/8; 011=f/6; 100=f/4; 101=f/3; 110=f/2; 111=f

CLKBX2

0 (Off)

Clock doubler for MCLKB

CLKAX2

0 (Off)

Clock doubler for MCLKA

44h

CLKMUX

0 (MCLKA)

Selects between MCLKA and MCLKB (N.B. On

power-up clock must be present on MCLKA and

must be active for 2 clock cycles after switching to

MCLKB)

Clock

Generation

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

15:1

N[3:0]

0000

PLL integer division control (must be set between 5-

12 for integer N mode)

0 = off

Allows PLL operation with low frequency input

clocks (< 8.192MHz)

SDM

Sigma Delta Modulator enable. Allows fractional N

division

DIVSEL

0 = off

Enables input clock to PLL to be divided by 2 or 4.

Use if input clock is above 14.4MHz

DIVCTL

Controls division mode when DIVSEL is high. 0 = div

by 2, 1= div by 4.

6:4

PGADDR

000

Pager address bits to access programming of

K[21:0] and SPLL[7:0]

46h

3:0

PGDATA

0000

Pager data bits

Analogue

Audio

Outputs,

Power-Up

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