CS5484 datasheet(32/67 Pages) CIRRUS

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CS5484

DS981F3

11 0101

Reserved

54*

11 0110

TGAIN

Temperature Gain

0x 06 B716

55*

11 0111

TOFF

Temperature Offset

0x D5 3998

56*

11 1000

Reserved

11 1001

TSETTLE

Filter Settling Time to Conv. Startup

0x 00 001E

58*

11 1010

LoadMIN

No-Load Threshold

0x 00 0000

59*

11 1011

Reserved

60*

11 1100

SYSGAIN

System Gain

0x 50 0000

11 1101

Time

System Time (in samples)

0x 00 0000

11 1110

Reserved

11 1111

Reserved

Notes:

(1) Warning: Do not write to unpublished or reserved register locations.

(2) * Registers with checksum protection.

** When setting the AVG_MODE bit (AVG_MODE = ‘1’) in the Config2 register, the device will

use the Line-cycle Synchronized Averaging mode and the CycleCount register will be includ-

ed in the checksum. Otherwise the SampleCount register will be included.

(3) Registers that can be set to write protect from DSP and/or HOST.

CS5484 Datasheet(PDF) 32 Page - Cirrus Logic

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