M32CSLASH8B datasheet(389/406 Pages) RENESAS

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Under development

M32C/8B Group

25. Usage Notes

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 372 of 385

25.8

DMAC

• Set the DMAC-associated registers while bits MDi1 and MDi0 (i = 0 to 3) in the channel i are set to 00b (DMA

disabled). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat transfer) at the end of the setup

procedure, which enables the DMA request of the channel i to be acknowledged.

• Write a 1 (requested) to the DRQ bit when setting the DMiSL register.

In the M32C/80 Series, if a DMA request is generated but a receiving channel is not ready(1), a DMA transfer does

not occur and the DRQ bit becomes 0.

NOTE:

1. Bits MDi1 and MDi0 are set to 00b or the DCTi register is 0000h (transferred 0 time).

• To start a DMA transfer using a software trigger, set bits DSR and DRQ in the DMiSL register to 1

simultaneously.

e.g.,

OR.B #0A0h, DMiSL

; set bits DSR and DRQ to 1 simultaneously

• While the DCTi register in the channel i is set to 1, do not generate a DMA request in the channel i in the timing

that bits MDi1 and MDi0 in the DMDj register (j = 0, 1) corresponding to the channel i are set to 01b (single

transfer) or 11b (repeat transfer). (Technical update: TN-M16C-88-0209)

• Select a peripheral function used as a DMA request source after setting the DMA-associated registers. When the

INT interrupt is selected as a DMA request source, do not set the DCTi register to 1.

• Wait six CPU clock cycles or more by a program to enable DMA after setting the DMiSL register(2).

NOTE:

2. To enable DMA means changing bits MDi1 and MDi0 in the DMDj register from 00b (DMA disabled)

to 01b (single transfer) or 11b (repeat transfer).

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