ADS58C48IPFPR datasheet(60/70 Pages) TI

60 / 70 page

S0444-01

CLKOUT

CHX_D0

ADS58C48

11-Bit Data

CHX_D1

CHX_D2

CHX_D9

CHX_D10

X = channels A, B, C and D

ADS58C48

SLAS689 – MAY 2010

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Parallel CMOS Interface

In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The rising

edge of the output clock CLKOUT can be used to latch data in the receiver.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade the

SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this,

the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures wide

data stable window provided the data outputs have minimal load capacitance. It is recommended to use short

traces (1 to 2 inches) terminated with not more than 5-pF load capacitance.

For sampling frequencies greater than 150 MSPS, it is recommended to use an external clock to capture data.

The delay from input clock to output data and the data valid times are specified for the higher sampling

frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data.

Figure 64. CMOS Interface

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ADS58C48IPFPR Datasheet(PDF) 60 Page - Texas Instruments