ADPD4100 datasheet(72/101 Pages) AD

72 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 72 of 101

Addr

Name

Bits

Bit Name

Description

Reset

Access

0x7: IN1 connected to VC2. IN2 connected to VC1.

0x8: IN1 floating. IN2 connected to VC1.

0x9: IN1 floating. IN2 connected to VC2.

0x0021 INPUT_CFG

[15:8]

Reserved

Reserved.

0x0

[7:6]

VC2_SLEEP

VC2 sleep state.

0x0

R/W

0: VC2 set to AVDD during sleep.

1: VC2 set to ground during sleep.

10: VC2 floating during sleep.

[5:4]

VC1_SLEEP

VC1 sleep state.

0x0

R/W

0: VC1 set to AVDD during sleep.

1: VC1 set to ground during sleep.

10: VC1 floating during sleep.

PAIR78

Input pair configuration.

0x0

R/W

0: IN7 and IN8 configured as two single-ended inputs.

1: IN7 and IN8 configured as a differential pair.

PAIR56

Input pair configuration.

0x0

R/W

0: IN5 and IN6 configured as two single-ended inputs.

1: IN5 and IN6 configured as a differential pair.

PAIR34

Input pair configuration.

0x0

R/W

0: IN3 and IN4 configured as two single-ended inputs.

1: IN3 and IN4 configured as a differential pair.

PAIR12

Input pair configuration.

0x0

R/W

0: IN1 and IN2 configured as two single-ended inputs.

1: IN1 and IN2 configured as a differential pair.

INTERRUPT STATUS AND CONTROL REGISTERS

Table 31. Interrupt Status and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access1

0x0000 FIFO_STATUS

CLEAR_FIFO

Clear FIFO. Write a 1 to empty the FIFO while the FIFO is

not being accessed. This resets FIFO_BYTE_COUNT and

clears the INT_FIFO_OFLOW, INT_FIFO_UFLOW, and

INT_FIFO_TH status bits.

0x0

R/W1C

INT_FIFO_UFLOW

FIFO underflow error. This bit is set when the FIFO is read

while empty. Write 1 to this bit to clear the interrupt. This

bit is also cleared if the FIFO is cleared using the

CLEAR_FIFO bit.

0x0

R/W1C

INT_FIFO_OFLOW

FIFO overflow error. This bit is set when data was not

written to the FIFO due to lack of space. Write 1 to this bit

to clear the interrupt. This bit is also cleared if the FIFO is

cleared with the CLEAR_FIFO bit.

0x0

R/W1C

[12:11] Reserved

Reserved.

0x0

[10:0]

FIFO_BYTE_COUNT

This field indicates the number of bytes in the FIFO.

0x0

0x0001 INT_STATUS_DATA

INT_FIFO_TH

FIFO_TH interrupt status. This bit is set during a FIFO

write when the number of bytes in the FIFO exceeds the

FIFO_TH register value. Write 1 to this bit to clear this

interrupt. This bit can also be automatically cleared when

the FIFO_DATA register is read if the INT_ACLEAR_FIFO

bit is set.

0x0

R/W1C

[14:12] Reserved

Reserved.

0x0

INT_DATA_L

Time Slot L data register interrupt status. This bit is set

every time the Time Slot L data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot L data registers

are read if the INT_ACLEAR_DATA_L bit is set.

0x0

R/W1C

ADPD4100 Datasheet(PDF) 72 Page - Analog Devices

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