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ADUC7023BCPZ62I-R7 Datasheet(PDF) 81 Page - Analog Devices

Part # ADUC7023BCPZ62I-R7
Description  Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler
PDF  98 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADUC7023BCPZ62I-R7 Datasheet(HTML) 81 Page - Analog Devices

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Data Sheet
ADuC7023
Rev. H | Page 81 of 98
IRQVEC Register
The IRQ interrupt vector register, IRQVEC, points to a
memory address containing a pointer to the interrupt service
routine of the currently active IRQ. This register should only be
read when an IRQ occurs and IRQ interrupt nesting has been
enabled by setting Bit 0 of the IRQCONN register.
IRQVEC Register
Name:
IRQVEC
Address:
0xFFFF001C
Default value:
0x00000000
Access:
Read only
Table 91. IRQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31 to 23
Read only
0
Always read as 0.
22 to 7
R/W
0
IRQBASE register value.
6 to 2
Read only
0
Highest priority source. This
is a value between 0 and 21
representing the possible
interrupt sources. For example,
if the highest currently active
IRQ is Timer 2, then these bits
are [00100].
1 to 0
Reserved
0
Reserved bits.
Priority Registers
The IRQ interrupt vector register, IRQVEC, points to a
memory address containing a pointer to the interrupt service
routine of the currently active IRQ. This register should only be
read when an IRQ occurs and IRQ interrupt nesting has been
enabled by setting Bit 0 of the IRQCONN register.



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