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M32C/8A Datasheet(PDF) 327 Page - Renesas Technology Corp |
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M32C/8A Datasheet(HTML) 327 Page - Renesas Technology Corp |
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327 / 372 page ![]() M32C/8A Group 23. Electrical Characteristics Rev.1.00 Jul 15, 2007 Page 310 of 352 REJ09B0385-0100 Table 23.25 Microprocessor Mode NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative. Symbol Parameter Standard Unit Min. Max. tac1(RD-DB) Data input access time (RD standard) (note 1) ns tac1(AD-DB) Data input access time (AD standard, CS standard) (note 1) ns tac2(RD-DB) Data input access time (RD standard, when accessing a space with the multiplexed bus) (note 1) ns tac2(AD-DB) Data input access time (AD standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(DB-BCLK) Data input setup time 26 ns tsu(RDY-BCLK) RDY input setup time 26 ns tsu(HOLD-BCLK) HOLD input setup time 30 ns th(RD-DB) Data input hold time 0 ns th(BCLK-RDY) RDY input hold time 0 ns th(BCLK-HOLD) HOLD input hold time 0 ns td(BCLK-HLDA) HLDA output delay time 25 ns 109 × m f(BCLK) × 2 - 35 [ns] (if external bus cycle is a φ + bφ, m = (b × 2) + 1) tac1(RD-DB) = 109 × n f(BCLK) - 35 [ns] (if external bus cycle is a φ + bφ, n = a + b) tac1(AD-DB) = 109 × m f(BCLK) × 2 - 35 [ns] (if external bus cycle is a φ + bφ, m = (b × 2) - 1) tac2(RD-DB) = 109 × p f(BCLK) × 2 - 35 [ns] (if external bus cycle is a φ + bφ, p = {(a + b - 1) × 2} + 1) tac2(AD-DB) = VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85 °C unless otherwise specified) |
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