LP55231 datasheet(28/53 Pages) TI

28 / 53 page

LP55231

SNOSCR5 – MARCH 2013

www.ti.com

Table 3. Control Register Map (continued)

Hex

Read/Writ

Default Value

Bit(s)

Bit Mnemonic and Description

Address

After Reset

THRESHOLD

Threshold voltage (typ.).

00 – 400mV

[7:6]

R/W

00xxxxxx

01 – 300mV

10 – 200mV

11 – 100mV

ADAPTIVE_THRESH_EN

[5]

R/W

xx0xxxxx

Activates adaptive threshold.

GAIN CHANGE CTRL

TIMER

00 – 5ms

[4:3]

R/W

xxx00xxx

01 – 10 ms

10 – 50 ms

11 – Infinite

FORCE_1x

[2]

R/W

xxxxx0xx

Activates 1.5x to 1x timer.

Control Register Details

00 ENABLE/ ENGINE CONTROL1

•

00 - Bit [6] CHIP_EN

•

1 = internal startup sequence powers up all the needed internal blocks and the device enters normal mode.

•

0 = standby mode is entered. Control registers can still be written or read, excluding bits[5:0] in reg 00 (this

•

00 — Bits [5:4] ENGINE1_EXEC

•

Engine 1 program execution control. Execution register bits define how the program is executed. Program

start address can be programmed to Program Counter (PC) register 37H.

•

00 = hold: Hold causes the execution engine to finish the current instruction and then stop. Program counter

(PC) can be read or written only in this mode.

•

01 = step: Execute the instruction at the location pointed by the PC, increment the PC by one and then reset

ENG1_EXEC bits to 00 (i.e. enter hold).

•

10 = free run: Start program execution from the location pointed by the PC.

•

11 = execute once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00 (i.e.

enter hold). The difference between step and execute once is that execute once does not increment the PC.

•

00 — Bits [3:2] ENGINE2_EXEC

•

Engine 2 program execution control. Equivalent to above definition of control bits. Program start address can

be programmed to Program Counter (PC) register 38H.

•

00 — Bits [1:0] ENGINE3_EXEC

•

Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can be

programmed to Program Counter (PC) register 39H.

01 ENGINE CONTROL2

•

Operation modes are defined in this register.

•

Disabled: Engines can be configured to disabled mode each one separately.

•

Load program: Writing to program memory is allowed only when the engine is in load program operation

mode and engine busy bit (reg 3A) is not set. Serial bus master should check the busy bit before writing to

program memory or allow at least 1ms delay after entering to load mode before memory write, to ensure

initalization. All the three engines are in hold while one or more engines are in load program mode. PWM

values are frozen, also. Program execution continues when all the engines are out of load program mode.

Load program mode resets the program counter of the respective engine. Load program mode can be

entered from the disabled mode only. Entering load program mode from the run program mode is not allowed.

•

Run Program: Run program mode executes the instructions stored in the program memory. Execution

Program start address can be programmed to the Program Counter (PC) register. The Program Counter is

reset to zero when the PC’s upper limit value is reached.

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