PC87366 datasheet(54/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.8.11

SuperI/O Configuration C Register (SIOCFC)

This is a battery-backed register.

Location:

Index 2Ch

Type:

R/W

Bit

76543210

Name

LED

Configura-

tion

Power LED

Status in

S4 or S5

LED2 Blink Rate

LED1 Blink Rate

Reset

00000000

Bit

Description

LED Conﬁguration

0: One dual-colored LED (default at VPP power-up reset)

1: Two LEDs

Power LED Status in S4 or S5. This bit is active only when hardware mode 2 is selected (bits 2-3 in the SIOCFB register).

0: Turn off (default at VDD power off)

1: Unchanged

5-3

LED2 Blink Rate

Bits

5 4 3

Rate

Duty Cycle

(Hz)

0 0 0

Off

Always low

0 0 1

0.25

12.5%

0 1 0

0.5

25%

0 1 1

50%Note 1.

1 0 0

50%

1 0 1

50%

1 1 0

50%

1 1 1

Always high (default at VPP power-up reset)

Note 1. When hardware mode 1 is selected, this rate will be set when VSB is powered up or when VDD becomes

inactive while VSB is active.

2-0

LED1 Blink Rate

Bits

2 1 0

Rate

Duty Cycle

(Hz)

0 0 0

Off

Always low (default at VPP power-up reset)

0 0 1

0.25

12.5%

0 1 0

0.5

25%

0 1 1

50%

1 0 0

50%

1 0 1

50%

1 1 0

50%

1 1 1

Always high

PC87366 Datasheet(PDF) 54 Page - National Semiconductor (TI)

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